`timescale 1ns/1ns
module t_Encoder8x3a;
  reg  [7:0] I;
  wire [2:0] Y;
  reg  clock;
  
  initial
  begin
   I[3:0]=8'd0;
   clock=1'b0;
  end
  always #5 clock = ~clock;
  
  always@(posedge clock) 
  begin
  I[7:4]= {$random}%16;
  I[3:0]= {$random}%16;
  end
  
  Encoder8x3a m1(
  .En(1'b1),
  .I(I),
  .Y(Y),
  .GS(1'b0));
endmodule

